Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic

ABSTRACT

A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function G I, I+1 =G I  OR G I+1  AND P I  is to be performed. When G I+1 =C I+1 , G I, I+1 =C I , arrival times of generate signals G I  and G I+1 , are investigated. If G I  arrives before G I+1 , a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function G I, I+1 ′=G I ′ AND G I+1 ′ OR P I ′ is to be performed. If the generate signal G I ′ arrives before G I+1 ′, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.

TECHNICAL FIELD

[0001] This invention relates generally to binary adder circuits and,more particularly, to fast binary adder circuits used in digitalprocessors.

BACKGROUND OF THE INVENTION

[0002] Modern processors (e.g., microprocessors) typically includeseveral binary adder circuits (i.e., “adders”). For example, one adderis typically used in an integer arithmetic logic unit (ALU) forperforming addition, subtraction, multiplication, and division. Afloating-point processor may include two adders: one for processing themantissa, and another for processing the exponents. Additional addersmay be used to compute relative addresses for memory access and branchinstructions.

[0003] In many processor designs, the speed of the processor is limitedby the time required to perform an addition operation in the ALU. Ingeneral, binary adders are performance-critical components of modernprocessors. Further, as processor clock signal frequencies increase andperiods decrease, implementing “wide” adders (e.g., 64-bit adders)capable of producing sums and carry signals during single cycles ofprocessor clock signals becomes increasingly difficult.

[0004] Although adders implemented in dynamic logic may compute sums andcarry signals faster than static logic implementations, static logicimplementations are still desirable due to the typical higher powerconsumption and the increased susceptibility to noise of dynamic logiccircuits.

[0005] The multiplicity of “fast” static adder designs includes carrylook ahead adders and carry select adders. In a typical carry look aheadadder, an addend A and an augend B are divided into multiple sections or“blocks” A_(I) and B_(I). In general, bits within each block, and acarry from a previous block (e.g., a carry in), are added to form a sumand a carry out for the block. Generate signals G_(I) and propagatesignals P_(I) are computed for each block, and logically combined tocompute the carry out:

[0006] P_(I)=A_(I)+B_(I) where ‘+’ represents logical OR (or alternatelyPI=AI XOR BI)

[0007] G_(I)=A_(I)·B_(I) where ‘·’ represents logical AND

[0008] Carry In=C_(I+1) (where lower numbered bits are more significant)

[0009] Carry Out=C_(I)=G_(I)+P_(I)·C_(I+1) (where lower numbered bitsare more significant)

[0010] Sum=A_(I) XOR B_(I) XOR C_(I) (or Sum=P_(I) XOR C_(I) whereP_(I)=A_(I) XOR B_(I))

[0011] The carry look ahead technique saves time by allowing carrysignal computations to be overlapped (i.e., by allowing the carrysignals to be computed substantially in parallel).

[0012] Carry select adders are also popular choices due to theirrelatively small gate fanouts (numbers of gate inputs driven by eachgate output) and relatively small numbers of gate stages compared withother static adder implementations (e.g., carry look ahead adders). In atypical carry select adder, as in the typical carry look ahead adder, anaddend A and an augend B are divided into multiple sections or blocks.In general, bits within each block, and a carry from a previous block(e.g., a carry in), are added to form a sum and a carry out for theblock.

[0013] Unlike the carry look ahead adder, the carry select adderperforms two separate addition operations for each block: one with acarry in (i.e., an assumed carry in) of ‘0’, and the other with a carryin (i.e., an assumed carry in) of ‘1’. The results of the two additionoperations are called “presums” and are typically provided to inputs ofa multiplexer. The carry out produced by the previous block is used tocontrol the multiplexer such that the multiplexer selects the correctpresum. The carry out produced by the previous block also determines thecarry out produced by the current block. The carry select techniquesaves time by computing all possible presums, then selecting from amongthe presums dependent upon the actual carry signals.

[0014] As processor clock signal frequencies continue to increase, acontinuing need exists for adders capable of producing sums and carrysignals in shorter periods of time.

SUMMARY OF THE INVENTION

[0015] A binary adder circuit is disclosed including a carry logiccircuit coupled to selection logic. The carry logic circuit receives agroup generate signal and a group propagate signal and produces a pairof complementary carry signals dependent upon the group generate signaland the group propagate signal. The selection logic receives a firstpresum, a second presum, and the pair of complementary carry signals,and produces either the first presum or the second presum dependent uponthe pair of complementary carry signals.

[0016] Methods are disclosed for producing a carry logic circuit for usein an adder circuit. The methods involve performing several operationsat each position along a critical timing path of the carry logiccircuit. In one method, a group generate logic function G_(I, I+1)=G_(I)OR G_(I+1) AND P_(I) is to be performed, where G_(I) and G_(I+1) aregenerate signals and P_(I) is a propagate signal. When G_(I+1)=C_(I+1,)then G_(I, I+1)=C_(I), and arrival times of the generate signals G_(I)and G_(I+1) are investigated. If the generate signal G_(I) arrivesearlier than the generate signal G_(I+1), a complex AND-OR-INVERT gateis selected to perform the group generate logic function. On the otherhand, if the generate signal G_(I+1) arrives earlier than the generatesignal G_(I), a cascaded pair of NAND gates is selected to perform thegroup generate logic function.

[0017] In another method, a group generate logic functionG_(I, I+1)′=G_(I)′ AND G_(I+1)′ OR P_(I)′ is to be performed, whereG_(I)′ and G_(I+1)′ are generate signals and P_(I)′ is a propagatesignal. The arrival times of the generate signals G_(I)′ and G_(I+1)′are investigated. If the generate signal G_(I)′ arrives earlier than thegenerate signal G_(I+1)′, a complex OR-AND-INVERT gate is selected toperform the group generate logic function. On the other hand, if thegenerate signal G_(I+1)′ arrives earlier than the generate signalG_(I)′, a cascaded pair of NOR gates is selected to perform the groupgenerate logic function.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify similar elements, and in which:

[0019]FIG. 1 is a diagram of one embodiment of a 64-bit binary addercircuit including multiple carry look ahead (CLA) adder circuits andstructures typical of carry select adder circuits;

[0020]FIG. 2 is a diagram of one embodiment of a representative one ofthe CLA adder circuits of FIG. 1, wherein the representative one of theCLA adder circuits includes CLA logic;

[0021]FIG. 3 is a diagram of one embodiment of the 64-bit adder circuitof FIG. 1; and

[0022]FIG. 4 is a diagram of one embodiment of the CLA logic of FIG. 2.

DETAILED DESCRIPTION

[0023] In the following discussion, numerous specific details are setforth to provide a thorough understanding of the present invention.However, those skilled in the art will appreciate that the presentinvention may be practiced without such specific details. In otherinstances, well-known elements have been illustrated in schematic orblock diagram form in order not to obscure the present invention inunnecessary detail. Additionally, for the most part, details concerningnetwork communications, electromagnetic signaling techniques, and thelike, have been omitted inasmuch as such details are not considerednecessary to obtain a complete understanding of the present invention,and are considered to be within the understanding of persons of ordinaryskill in the relevant art.

[0024] It is further noted that, unless indicated otherwise, allfunctions described herein may be performed in either hardware orsoftware, or some combination thereof. In a preferred embodiment,however, the functions are performed by a processor, such as a computeror an electronic data processor, in accordance with code, such ascomputer program code, software, and/or integrated circuits that arecoded to perform such functions, unless indicated otherwise.

[0025]FIG. 1 is a diagram of one embodiment of a 64-bit binary addercircuit 100 including both carry look ahead (CLA) structures and carryselect structures. Adder circuit 100 receives a 64-bit binary addendA<0:63>, a 64-bit binary augend B<0:63>, and a CARRY IN signal, andproduces a 64-bit binary sum SUM<0:63> and a CARRY OUT signal such that:

[0026] SUM<0:63>=A<0:63>+B<0:63>+CARRY IN (‘+’ represents addition) andthe CARRY OUT signal is set if the addition operation produces a carry.

[0027] It is noted that in the ordered bit representations describedherein, a <0> bit is the most significant bit, and the highest numberedbit (e.g., bit <63>) is the least significant bit. For example, thedecimal value represented by the 64-bit binary addend A<0:63> is equalto (A<0>·2⁶³)+(A<1>·2⁶²)+ . . . +(A<63>·2⁰), where ‘+’ representsaddition and ‘·’ represent multiplication.

[0028] In the embodiment of FIG. 1, the 64-bit adder circuit 100includes 15 substantially identical versions of an 8-bit carry lookahead (CLA) adder circuit 102. Fourteen of the CLA adder circuits 102are arranged to form seven pairs of CLA adder circuits. To simplify FIG.1, only two of the pairs (labeled 104A and 104B) are shown in FIG. 1.The fifteenth CLA adder circuit operates alone, and is labeled 106 inFIG. 1. The seven pairs of CLA adder circuits receive the seven mostsignificant 8-bit portions (i.e., “slices”) of the addend A<0:63> andthe augend B<0:63>, and the lone CLA adder circuit 106 receives theeighth least significant 8-bit slice of the addend A<0:63> and theaugend B<0:63>.

[0029] In the pair 104A, each of the CLA adder circuits 102 receivesA<0:7> and B<0:7> and a carry in signal CIN, and produces a presumS<0:7>, where S<0:7>=A<0:7>+B<0:7>+CIN (‘+’ represents addition). In CLAfashion, one of the CLA adder circuits 102 of the pair 104A alsoproduces a propagate signal P₀₇ ⁰ and a generate signal G₀₇ ⁰. (Theother CLA adder circuit 102 of the pair 104A may also produce thepropagate signal P₀₇ ⁰ and the generate signal G₀₇ ⁰, but only one ofthe CLA adder circuits 102 of the pair 104A need generate the propagatesignal P₀₇ ⁰ and the generate signal G₀₇ ⁰). As described in more detailbelow, the carry logic 108 receives the propagate signal P₀₇ ⁰ and thegenerate signal G₀₇ ⁰, and uses the P₀₇ ⁰ and G₀₇ ⁰ signals to producethe CARRY OUT signal.

[0030] In carry select fashion, the carry in signal CIN to one of theCLA adder circuits 102 of the pair 104A is a ‘0’, and the carry insignal CIN to the other CLA adder circuit 102 is a ‘1’. Both of the CLAadder circuits 102 provide their presums S<0:7> to inputs of amultiplexer 110A. The multiplexer 110A receives complementary carrysignals (i.e., “hot” carry signals) C8 and C8N, where C8N=C8′, uses thecomplementary hot carry signals C8 and C8N to select one of the presumsS<0:7> produced by the CLA adder circuits 102 of the pair 104A, andproduces the selected presum S<0:7> as SUM<0:7> for the adder circuit100.

[0031] Similarly, in the pair 104B, each of the CLA adder circuits 102receives A<8:15> of the addend as A<0:7>, B<8:15> of the augend asB<0:7>, and a carry in signal CIN, and produces a presum S<0:7>, whereS<0:7>=A<0:7>+B<0:7>+CIN (‘+’ represents addition). In CLA fashion, oneof the CLA adder circuits 102 of the pair 104B also produces a propagatesignal P₀₇ ¹ and a generate signal G₀₇ ¹. As described in more detailbelow, the carry logic 108 receives the propagate signal P₀₇ ¹ and thegenerate signal G₀₇ ¹, and uses the P₀₇ ¹ and G₀₇ ¹ signals to producethe complementary hot carry signals C8 and C8N.

[0032] In carry select fashion, the carry in signal CIN to one of theCLA adder circuits 102 of the pair 104B is a ‘0’, and the carry insignal CIN to the other CLA adder circuit 102 is a ‘1’. Both of the CLAadder circuits 102 of the pair 104B provide their presums S<0:7> toinputs of a multiplexer 110B. The multiplexer 110B receivescomplementary hot carry signals C16 and C16N, where C16N=C16′, uses thecomplementary hot carry signals C16 and C16N to select one of thepresums S<0:7> produced by the CLA adder circuits 102 of the pair 104B,and produces the selected presum S<0:7> as SUM<8:15> for the addercircuit 100.

[0033] The CLA adder circuit 106 receives A<56:63> of the addend asA<0:7>, B<56:63> of the augend as B<0:7>, and the CARRY IN signal to theadder circuit 100 as a carry in signal CIN, and produces a (final) sumS<0:7>, where S<0:7>=A<0:7>+B<0:7>+CIN (‘+’ represents addition). Asindicated in FIG. 1, the sum S<0:7> produced by the CLA adder circuit106 becomes SUM <56:63> for the adder circuit 100. The CLA adder circuit106 also produces a propagate signal P₀₇ ⁷ and a generate signal G₀₇ ⁷.As described in more detail below, the carry logic 108 receives thepropagate signal P₀₇ ⁷ and the generate signal G₀₇ ⁷, and uses the P₀₇ ⁷and G₀₇ ⁷ signals to produce complementary hot carry signals C56 andC56N.

[0034] The carry logic 108 receives the CARRY IN signal to the addercircuit 100, the seven p₀₇ ^(K) signals produced by the seven pairs ofCLA adder circuits (0≦K≦6), and the P₀₇ ⁷ and G₀₇ ⁷ signals produced bythe CLA adder circuit 106, and uses the CARRY IN signal and thepropagate and generate signals to produce complementary hot carrysignals C8 and C8N, C16 and C16N, C24 and C24N, C32 and C32N, C40 andC40N, C48 and C48N, and C56 and C56N, where:

[0035] C8=G₀₇ ¹+P₀₇ ¹·C16, where ‘+’ represents logical OR and ‘·’represents logical AND,

[0036] C16=G₀₇ ²+P₀₇ ²·C24,

[0037] C24=G₀₇ ³+P₀₇ ³·C32,

[0038] C32=G₀₇ ⁴+P₀₇ ⁴·C40,

[0039] C40=G₀₇ ⁵+P₀₇ ⁵·C48,

[0040] C48=G₀₇ ⁶+P₀₇ ⁶·C56, and

[0041] C56=G₀₇ ⁷+P₀₇ ⁷·CIN.

[0042] The carry logic 108 also uses the CARRY IN signal and thepropagate and generate signals to generate a carry out signal CO, andproduces the CO signal as the CARRY OUT signal of the adder circuit 100:

[0043] CARRY OUT=CO=G₀₇ ⁰+P₀₇ ⁰·C8(‘+’=OR, ‘·’=AND)

[0044]FIG. 2 is a diagram of one embodiment of the CLA adder circuit 102of FIG. 1. In the embodiment of FIG. 2, the CLA adder circuit 102includes eight propagate-generate (PG) cells. To simplify FIG. 2, onlythree of the eight PG cells (labeled 200A-200C) are shown in FIG. 2. TheCLA adder circuit 102 also includes a CLA logic unit 202 and eight sumlogic units. To simplify FIG. 2, only three of the eight sum logic units(labeled 204A-204C) are shown in FIG. 2. As indicated in FIG. 2, the CLAadder circuit 102 receives an 8-bit portion (i.e., “slice”) A<K:K+7> ofthe addend (K=0, 8, . . . , 56), a corresponding 8-bit slice B<K:K+7> ofthe augend, and a carry in signal CIN, and produces an 8-bit sum (presumor final sum) S<K:K+7> such that:

[0045] S<K:K+7>=A<K:K+7>+B<K:K+7>+CIN (‘+’ represents addition)

[0046] As indicated in FIG. 2, each of the PG cells 200 receives acorresponding bit A<M> of A<K:K+7>, where (0<M<7), and a correspondingbit B<M> of B<K:K+7>, produces an inverted propagate signal PN<M> and aninverted generate signal GN<M> such that:

[0047] PN<M>=A<M> NOR B<M>, and

[0048] GN<M>=A<M> NAND B<M>.

[0049] It is noted that since PN<M>=P<M>′ and GN<M>=G<M>′:

[0050] P<M>=A<M> OR B<M>, and

[0051] G<M>=A<M> AND B<M>.

[0052] and that, in other embodiments, each of the PG cells 200 may alsoproduce the propagate signal P<M> and the generate signal G<M> suchthat:

[0053] P<M>=A<M> OR B<M>, and

[0054] G<M>=A<M> AND B<M>.

[0055] The CLA logic unit 202 receives the inverted propagate signalsPN<M> and the inverted generate signals GN<M> produced by the eight PGcells 200 and a carry in signal CIN, and produces carry signals C<0>through C<7> such that:

[0056] C<7>=CIN, and

[0057] C<M>=G<M>+P<M>·C<M+1>, where 0≦M≦6, G<M>=GN<M>′, P<M>=PN<M>′,‘+’=OR, and ‘·’=AND.

[0058] The CLA logic unit 202 also produces a propagate signal P₀₇^(K/8) and a generate signal G₀₇ ^(K/8) where:

[0059] P₀₇ ^(K/8)=P<0>·P<1>·P<2>·P<3>·P<4>·P<5>P<·6>·P<7>, whereP<N>=PN<N>′ and ‘·’=AND, and

[0060] G₀₇^(K/8)=G<0>+G<1>·P<0>+G<2>·P<1>·P<0>+G<3>·P<2>·P<1>·P<0>+G<4>·P<3>·P<2>·P<1>·P<0>+G<5>·P<4>·P<3>·P<2>·P<1>·P<0>+G<6>·P<5>·P<4>·P<3>·P<2>·P<1>·P<0>+G<7>·P<6>·P<5>·P<4>·P<3>·P<2>·P<1>·P<0>,where G<N>=GN<N>′, P<N>=PN<N>′, ‘+’=OR, and ‘·’=AND.

[0061] Each of the sum logic units 204 receives a corresponding bit A<M>of A<K:K+7>, where (0≦M≦7), a corresponding bit B<M> of B<K:K+7>, andthe corresponding carry signal C<M> from the carry logic unit 202,produces a sum bit (presum bit or final sum bit) S<M> such that:

[0062] S<M>=A<M>XOR B<M>XOR C<M>, where XOR represents logical exclusiveOR

[0063]FIG. 3 is a diagram of one embodiment of the 64-bit adder circuit100 of FIG. 1. In the embodiment of FIG. 3, an 8-bit adder circuitlabeled “8b ADD” and receiving A<56:63> and B<56:63> represents the CLAadder circuit 106 of FIG. 1. The other seven 8-bit adder circuitslabeled “8b ADD” in FIG. 3 each include a pair of CLA adder circuits 104of FIG. 1 and the corresponding multiplexer 110 of FIG. 1.

[0064] The carry logic 108 of FIG. 1 is distributed among four carrylogic units labeled “carry logic 1,” “carry logic 2,” “carry logic 3,”and “carry logic 4” in FIG. 3, and a section labeled 300 includingseveral logic gates. The logic gates within the carry logic units “carrylogic 1,” “carry logic 2,” “carry logic 3,” and “carry logic 4” are notshown to simplify FIG. 3. As indicated in FIG. 3 and described above,the complementary hot carry signals C8 and C8N, C16 and C16N, C24 andC24N, C32 and C32N, C40 and C40N, C48 and C48N, and C56 and C56N, aregenerated by the distributed carry logic and used to select betweenpresums generated by the CLA adder circuits in carry-select fashion. Ingeneral, the adder circuit 100 of FIGS. 1 and 3 include dual hot carrynetworks providing complementary hot carry signals.

[0065] In general, within the carry logic units “carry logic 1,” “carrylogic 2,” “carry logic 3,” and “carry logic 4,” and the section labeled302, propagate signals P_(I) and P_(I+1) and generate signals G_(I) andG_(I+1) are logically combined several times such that:

[0066] P_(I, I+1)=P_(I)·P_(I+1) (‘·’ represents logical AND)

[0067] G_(I, I+1)=G_(I)+G_(I+1)·P_(I) (‘+’ represents logical OR and ‘·’represents logical AND)

[0068] Herein below, the logic function P_(I, I+1)=P_(I)·P_(I +1) willbe referred to as a “group propagate logic function,” and the logicfunction G_(I, I+1)=G_(I)+G_(I+1)·P_(I) will be referred to as a “groupgenerate logic function.”

[0069] Several of the complementary hot carry signals are generatedwithin the section 300, and a critical timing path (i.e., “criticalpath”) of the adder circuit 100 resides substantially within the section300. In the embodiment of FIG. 3, the carry logic includes multiplepairs of signal lines 302 within the section 300 and positioned alongthe critical path of the adder circuit 100. Each of the pairs of signallines 302 is used to convey complementary hot carry signals within thesection 300.

[0070] The logic gates used to carry out the logic functions within thesection 300 have been analyzed and optimized with regard to timing suchthat the adder circuit produces the 64-bit sum SUM<0:63> and the CARRYOUT signal in less time. Specifically, the section 300 has been formedby carefully selecting between complex complementary metal oxidesemiconductor (CMOS) AND-OR-INVERT (AOI) gates and OR-AND-INVERT (OAI),and NAND/NOR gate combinations, to perform carry logic functions. Ingeneral, where a carry logic function is to be performed, a complexAOI/OAI gate or a NAND/NOR gate combination is selected based on signalarrival times.

[0071] Within the section 300 of FIG. 3, the following logic operationsare performed at several locations along the critical path of the carrylogic circuit of the adder circuit 100:

[0072] G_(I, I+1)=G_(I)+G_(I+1)·P_(I) (‘+’ represents logical OR and ‘·’represents logical AND), and

[0073] G_(I, I+1)′=G_(I)′·G_(I+1)′+P_(I)′.

[0074] A carry look ahead adder circuit normally produces a propagatesignal P_(I) before a generate signal G_(I), thus group generatefunctions and arrival times of generate signals G_(I) and G_(I+1) arescrutinized.

[0075] To produce group generate signals as quickly as possible, when agenerate signal G_(I)/G_(I)′ arrives earlier than a generate signalG_(I+1)/G_(I+1)′, a complex AOI/OAI gate is preferably used to performthe group generate logic function. On the other hand, when the generatesignal G_(I+1)/G_(I+1)′ arrives earlier than the generate signalG_(I)/G_(I)′, a cascaded pair of 2-input NAND/NOR gates is preferablyused to perform the group generate logic function. The propagate signalP_(I)/P_(I)′ and the earlier arriving generate signal G_(I+1)/G_(I+1)′are preferably provided to the two inputs of a first of the NAND/NORgates, and the later arriving generate signal G_(I)/G_(I)′ is preferablyprovided to one input of the second NAND/NOR gate.

[0076] For example, in FIG. 3, a NAND-NAND gate combination 304 performsthe logical function:

[0077] g4063=((g56c NAND p4055) NAND g4055n)

[0078] A timing analysis revealed the generate signal g56c (G_(I+1))arrived earlier than the generate signal g4055n (G_(I)′). In accordancewith the above gate selection process, the NAND-NAND gate combination304 was selected over a logically equivalent AOI gate. The propagatesignal p4055 (P_(I)) and the earlier arriving generate signal g56c(G_(I+1)) are provided to the two inputs of a first NAND gate of theNAND-NAND gate combination 304, and the later arriving generate signalg4055n (G_(I)′) is provided to one input of the second NAND gate of theNAND-NAND gate combination 304. It is noted that the resulting generatesignal g4063 is the hot carry signal C40 formed over bits <40:63> of theaddend and the augend.

[0079] A NOR-NOR gate combination 306 in FIG. 3 performs the logicalfunction:

[0080] g4063n=((g56cn NOR p4055n) NOR g4055)

[0081] A timing analysis revealed the generate signal g56cn (G_(I+1)′)arrived earlier than the generate signal g4055 (G_(I)). In accordancewith the above gate selection process, the NOR-NOR gate combination 306was selected over a logically equivalent OAI gate. The propagate signalp4055n (P_(I)′) and the earlier arriving generate signal g56cn(G_(I+1)′) are provided to the two inputs of a first NOR gate of theNOR-NOR gate combination 306, and the later arriving generate signalg4055 (G_(I)) is provided to one input of the second NOR gate of theNOR-NOR gate combination 306. It is noted that the resulting invertedgenerate signal g4063n is the hot carry signal C40N, the complement ofthe hot carry signal C40 produced by the NAND-NAND gate combination 304.

[0082] Similarly, a NAND-NAND gate combination 308 in FIG. 3 wasselected as the carry in signal cin arrives earlier than the generatesignal g5663n, and a NOR-NOR gate combination 310 was selected as thesignal cinn (cin′) arrives earlier than the generate signal g5663.

[0083] An AOI gate 312 in FIG. 3 performs the logical function:

[0084] c8n=((g4063 AND p839) OR g839)

[0085] A timing analysis revealed the generate signal g839 (G_(I))arrived earlier than the generate signal g4063 (G_(I+1)). In accordancewith the above gate selection process, the AOI gate 312 was selectedover a logically equivalent NAND-NAND gate combination.

[0086] The generation and distribution complementary hot carry signals,combined with the careful selection of AOI/OAI gates and NAND/NOR gatecombinations along the critical path of the carry logic of FIG. 3,resulted in a 10% reduction in the amount of time required to producethe 64-bit sum and carry out signal (CO in FIG. 3). At the same time, amaximum gate size in the carry logic was reduced by 50%, while a totalarea required to implement the adder circuit 100 remained substantiallythe same.

[0087] It is noted that in the interest of structural regularity, all ofthe 8-bit adder circuits of the adder circuit 100 may be madesubstantially identical. That is, all of the 8-bit adder circuits of theadder circuit 100 may be produced with similar feature sizes (i.e.,device sizes). However, additional reductions in the amount of timerequired to produce the 64-bit sum and carry out signal are possiblewhen devices in each of the 8-bit adder circuits are selectively sized.

[0088]FIG. 4 is a diagram of one embodiment of the CLA logic 202 of FIG.2. Group generate and propagate logic functions are also performed inthe CLA logic unit 202, and the above gate replacement approach has alsobeen applied to the CLA logic unit 202 of FIG. 4.

[0089] For example, a NOR-NOR gate combination 402 in FIG. 4 performsthe logical function:

[0090] g01n=((gn<1> NOR pn<0>) NOR g<0>)

[0091] A timing analysis revealed the generate signal gn<1> (G_(I+1)′)arrived earlier than the generate signal g<0> (G_(I)). In accordancewith the above gate selection process, the NOR-NOR gate combination 402was selected over an OAI gate. The propagate signal pn<0> (P_(I)′) andthe earlier arriving generate signal gn<1> (G_(I+1)′) are provided tothe two inputs of a first NOR gate of the NOR-NOR gate combination 402,and the later arriving generate signal g<0> (G_(I)) is provided to oneinput of the second NOR gate of the NOR-NOR gate combination 402.

[0092] Similarly, a NOR-NOR gate combination 404 in FIG. 4 was selectedover a logically equivalent OAI gate for the reasons described above,and NAND-NAND gate combinations 406, 408, and 410 were selected overlogically equivalent AOI gates during the gate selection process.

[0093] The particular embodiments disclosed above are illustrative only,as the invention may be modified and practiced in different butequivalent manners apparent to those skilled in the art having thebenefit of the teachings herein. Furthermore, no limitations areintended to the details of construction or design herein shown, otherthan as described in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

What is claimed is:
 1. A binary adder circuit, comprising: a carry logiccircuit coupled to receive a group generate signal and a group propagatesignal and configured to produce a pair of complementary carry signalsdependent upon the group generate signal and the group propagate signal;and selection logic coupled to receive a first presum, a second presum,and the pair of complementary carry signals, and configured to produceeither the first presum or the second presum dependent upon the pair ofcomplementary carry signals.
 2. The binary adder circuit as recited inclaim 1, wherein the carry logic circuit comprises a pair of signallines used to convey complementary generate signals, and wherein one ofthe complementary generate signals is used to produce one of the pair ofcomplementary carry signals, and wherein the other complementarygenerate signal is used to produce the other of the pair ofcomplementary carry signals.
 3. The binary adder circuit as recited inclaim 2, wherein the carry logic circuit comprises a plurality of pairsof signal lines used to convey complementary hot carry signals.
 4. Thebinary adder circuit as recited in claim 3, wherein the plurality ofpairs of signal lines are positioned along a critical timing path of thebinary adder circuit.
 5. The binary adder circuit as recited in claim 1,wherein the carry logic circuit comprises a cascaded pair of NAND gatesdriving one of a pair of signal lines used to convey complementary hotcarry signals.
 6. The binary adder circuit as recited in claim 1,wherein the carry logic circuit comprises a cascaded pair of NOR gatesdriving one of a pair of signal lines used to convey complementary hotcarry signals.
 7. The binary adder circuit as recited in claim 1,wherein the carry logic circuit comprises a cascaded pair of NAND gatesdriving one of a pair of signal lines used to convey complementary hotcarry signals, and a cascaded pair of NOR gates driving the other of thepair of signal lines used to convey complementary hot carry signals. 8.The binary adder circuit as recited in claim 1, further comprising acarry look ahead (CLA) adder circuit coupled to receive a portion of anaddend and a corresponding portion of an augend, and configured toproduce the group generate signal and the group propagate signal.
 9. Thebinary adder circuit as recited in claim 1, wherein the portion of theaddend and the portion of the augend comprise a plurality of orderedpairs of bits, and wherein the CLA adder circuit is configured toproduce a local generate signal and a local propagate signal for each ofthe ordered pairs of bits, and wherein the group propagate signal is aproduct of the local propagate signals, and wherein the group generatesignal is a sum of products of the local generate and propagate signals.10. The binary adder circuit as recited in claim 1, further comprising apair of carry look ahead (CLA) adder circuits, wherein one of the pairof CLA adder circuits is configured to produce the first presum and theother of the pair of CLA adder circuits is configured to produce thesecond presum.
 11. The binary adder circuit as recited in claim 1,wherein the selection logic comprises a multiplexer.
 12. A binary addercircuit, comprising: a first carry look ahead (CLA) adder circuitcoupled to receive a first portion of an addend and a correspondingfirst portion of an augend, and configured to produce a group generatesignal and a group propagate signal; a second CLA adder circuit and athird CLA adder circuit each coupled to receive a second portion of theaddend and a corresponding second portion of the augend, wherein thesecond CLA adder circuit is configured to produce a first presum and thethird CLA adder circuit is configured to produce a second presum; acarry logic circuit coupled to receive the group generate signal and thegroup propagate signal and configured to produce a pair of complementarycarry signals dependent upon the group generate signal and the grouppropagate signal; and a multiplexer coupled to receive a first presum, asecond presum, and the pair of complementary carry signals, andconfigured to produce either the first presum or the second presumdependent upon the pair of complementary carry signals.
 13. The binaryadder circuit as recited in claim 12, wherein the carry logic circuitcomprises a pair of signal lines used to convey complementary generatesignals, and wherein one of the complementary generate signals is usedto produce one of the pair of complementary carry signals, and whereinthe other complementary generate signal is used to produce the other ofthe pair of complementary carry signals.
 14. The binary adder circuit asrecited in claim 13, wherein the carry logic circuit comprises aplurality of pairs of signal lines used to convey complementary hotcarry signals.
 15. The binary adder circuit as recited in claim 14,wherein the plurality of pairs of signal lines are positioned along acritical timing path of the binary adder circuit.
 16. The binary addercircuit as recited in claim 12, wherein the carry logic circuitcomprises a cascaded pair of NAND gates driving one of a pair of signallines used to convey complementary hot carry signals.
 17. The binaryadder circuit as recited in claim 12, wherein the carry logic circuitcomprises a cascaded pair of NOR gates driving one of a pair of signallines used to convey complementary generate signals.
 18. The binaryadder circuit as recited in claim 12, wherein the carry logic circuitcomprises a cascaded pair of NAND gates driving one of a pair of signallines used to convey complementary generate signals, and a cascaded pairof NOR gates driving the other of the pair of signal lines used toconvey complementary generate signals.
 19. A method for producing acarry logic circuit for use in an adder circuit, comprising: performingthe following operations at each position along a critical timing pathof the carry logic circuit where a group generate logic functionG_(I, I+1)=G_(I) OR G_(I+1) AND P_(I) is to be performed, wherein G_(I)and G_(I+1) are generate signals and P_(I) is a propagate signal:determining arrival times of the generate signals G_(I) and G_(I+1) atthe position; in the event the generate signal G_(I) arrives earlierthan the generate signal G_(I+1), selecting a complex AND-OR-INVERT gateto perform the group generate logic function; and in the event thegenerate signal G_(I+1) arrives earlier than the generate signal G_(I),selecting a cascaded pair of NAND gates to perform the group generatelogic function.
 20. The method as recited in claim 19, furthercomprising: in the event the generate signal G_(I+1) arrives earlierthan the generate signal G_(I), providing the propagate signal P_(I) andthe earlier arriving generate signal G_(I+1) to inputs of a first of thecascaded pair of NAND gates, and providing the later arriving generatesignal G_(I) to an input of the second of the cascaded pair of NANDgates.
 21. A method for producing a carry logic circuit for use in anadder circuit, comprising: performing the following operations at eachposition along a critical timing path of the carry logic circuit where agroup generate logic function G_(I, I+1)′=G_(I)′ AND G_(I+1)′ OR P_(I)′is to be performed, wherein G_(I)′ and G_(I+1)′ are generate signals andP_(I)′ is a propagate signal: determining arrival times of the generatesignals G_(I)′ and G_(I+1)′ at the position; in the event the generatesignal G_(I)′ arrives earlier than the generate signal G_(I+1)′,selecting a complex OR-AND-INVERT gate to perform the group generatelogic function; and in the event the generate signal G_(I+1)′ arrivesearlier than the generate signal G_(I)′, selecting a cascaded pair ofNOR gates to perform the group generate logic function.
 22. The methodas recited in claim 21, further comprising: in the event the generatesignal G_(I+1)′ arrives earlier than the generate signal G_(I)′,providing the propagate signal P_(I)′ and the earlier arriving generatesignal G_(I+1)′ to inputs of a first of the cascaded pair of NOR gates,and providing the later arriving generate signal G_(I)′ to an input ofthe second of the cascaded pair of NOR gates.